integrated circuit systems, inc. general description features ics9169c-232 block diagram frequency generator for pentium? based systems 9169c-232revb031897 pin configuration 28-pin soic or ssop functionality 3.3v10%, 0-70 c crystal (x1, x2) = 14.31818 mhz pentium is a trademark of intel corporation. ? strong output drive. ? eight selectable cpu clocks operate up to 83.3 mhz ? frequency selections inc lude t urbo-mode speed of 68.5 mhz ? maximum cpu jitter of 200ps ? six bus clocks support sync or async bus operation ? 250ps skew window for cpu outputs, 500ps skew window for bus outputs ? cpu clocks to bus clocks skew 1-4 ns (cpu early) ? 48 mhz clock for usb support & 24 mhz clock for fd. ? logic inputs latched at power-on for frequency selection saving pins as input/output ? integrated buffer outputs drive up to 30pf loads ? 3.0v - 3.7v supply range, cpu (1:6) outputs 2.5v (2.375 - 2.6v) vdd option ? 28-pin soic or ssop package the ics9169c-232 is a low-cost frequency generator designed specifically for pentium and pentium-pro based chip set systems. the integrated buffer minimizes skew and provides all the clocks required. a 14.318 mhz xtal oscillator provides the reference clock to generate standard pentium frequencies. the cpu clock makes gradual frequency transitions without violating the pll timing of internal microprocessor clock multipliers. a raised frequency setting of 68.5 mhz is available for turbo-mode of the 66.8 mhz cpu. the ics9169c-232 contains 8 cpu clocks, 6 pci clocks, 1 ref at 48mhz and 1 at 24mhz. either synchronous (cpu/2) or asynchronous (32 mhz) pci bus operation can be selected by latching data on bsel input. address select cpu(1:8) (mhz) bus (1:6)mhz 48mhz 24mhz ref fs2 fs1 fs0 bsel=1 bsel=0 0005025324824ref 0016030324824ref 0 1 0 66.8 33.4 32 48 24 ref 01 1 75.9 32 32 48 24ref 10 0 55 27.5 32 48 24ref 1 0 1 75.9 37.5 32 48 24 ref 1 1 0 83.3 41.7 32 48 24 ref 1 1 1 68.5 34.25 32 48 24 ref vdd groups: vdd1 = x1, x2, ref/bsel vdd2 = cpu1-6 vdd3 = cpu7-8 & pll core vdd4 = bus1-6 vdd5 = 48/24 mhz latched inputs: l1 = bsel l2 = fs0 l3 = fs1 l4 = fs2 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics169c-232 pin descriptions pin number pin name type description 1 vdd1 pwr power for control logic and crystal oscillator circuit and 14.318 mhz output 2x1 in xtal or external reference frequency input. this input includes xtal load capacitance and feedback bias for a 12-16mhz crystal, nominally 14.31818mhz. external crystal load of 30pf to gnd recommended for vdd power on faster than 2.0ms. 3 x2 out xtal output which includes xtal load capacitance. external crystal load of 10pf to gnd recommended for vdd power on faster than 2.0ms. 4,11,16,22 gnd pwr ground for control logic. 6,7,9,10,15 cpu(2,3,4,5,8) out processor clock outputs which are a multiple of the i nput reference clock as shown in the preceding table. 5,12,13 cpu1, cpu6, cpu7 out processor clock outputs which are a multiple of the i nput reference clock as shown in the preceding table. 5,12,13 fs (0:2) in frequency multiplier select pins. see shared pin programming description later in this data sheet for further explanation. 350k* internal pull up. 8 vdd2 pwr power for cpu (1:6) clock buffers only. this vdd s upply can be reduced to 2.5v for cpu (1:6) outputs. 14 vdd3 pwr power for cpu (7:8) clock buffers and internal pll and core logic. must be nominal 3.3v (3.0 to 3.7v) 17,18,20,21,23, 24 bus(1:6) out bus clock outputs which are a multiple of the i nput reference clock as shown in the preceding table. 19 vdd4 pwr power for bus clock buffers bus (1;6) 25 vdd5 pwr power for fixed clock buffer (48 mhz, 24 mhz) 26 24 mhz out fixed 24 mhz clock (assuming a 14.31818 mhz ref frequency). 27 48 mhz out fixed 48 mhz clock (assuming a 14.31818 mhz ref frequency). 28 ref out fixed 14.31818 mhz clock (assuming a 14.31818 mhz ref frequency). bsel in selection for synchronous or asynchronous bus clock operation. 350k* internal pull up. * the internal pull up will vary from 350k to 500k based on temperature
3 ics169c-232 fig. 1 shared pin operation - input/output, pins 5, 28, 12 and 13 on the ics9169c-232 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. at the end of power-on reset, (see ac char acteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm(10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. figs. 1 and 2 show the recommended means of implementing this function. in fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the devices internal logic. figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. these figures illustrate the optimal pcb physical layout options. these configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. the layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s). shared pin operation - input/output pins the ics9169c-232 includes a production test verification mode of operation. this requires that the fs0 and fs1 pins be programmed to a logic high and the fs2 pin be programmed to a logic low(see shared pin operation section). in this mode the device will output the following frequencies. note: ref is the frequency of either the crystal connected between the devices x1and x2 or, in the case of a device being driven by an external reference clock, the frequency of the reference (or test) clock on the devices x1 pin. test mode operation pin frequency ref ref 48mhz ref/2 24mhz ref/4 cpu (1:8) ref2 bus (1:6) bsel=1 ref/4 besel = 0 ref/3
4 ics169c-232 fig. 2a fig. 2b fig. 3
5 ics169c-232 technical pin function descriptions vdd1 this is the power supply to the internal logic of the device as well as the following clock output buffers: a. ref clock output buffers b. bus clock output buffers c. fixed clock output buffers this pin may be operated at any voltage between 3.0 and 5.5 volts. clocks from the listed buffers that it supplies will have a voltage swing from ground to this level. for the actual guaranteed high and low voltage levels of these clocks, please consult the ac parameter table in this data sheet. gnd this is the power supply ground return pin for the internal logic of the device as well as the following clock output buffers: a. ref clock output buffers b. bus clock output buffers c. cpu clock output buffers x1 this pin serves one of two functions. when the de vice is used with a crystal, x1 acts as the input pin for the reference signal that comes from the discrete crystal. when the device is driven by an external clock signal, x1 is the device input pin for that reference clock. this pin also implements an internal crystal loading capacitor that is connected to ground. see the data tables for the value of the capacitor. x2 this pin is used only when the device uses a crystal as the reference frequency source. in this mode of operation, x2 is an output signal that drives (or excites) the discrete crystal. this pin also implements an internal crystal loading capacitor that is connected to ground. see the data tables for the value of the capacitor. cpu (1:8) this pin is the clock output that drives processor and other cpu related circuitry that require clocks which are in tight skew tolerance with the cpu clock. the voltage swing of these clocks is controlled by that which is applied to the vdd pin of the device. see the functionality table at the beginning of this data sheet for a list of the specific frequencies this clock operates at and the selection codes that are necessary to produce these frequencies. bus (1:6) this pin is the clock output that is intended to drive the systems plug-in card bus. the voltage swing of these clocks is controlled by the supply that is applied to the vdd pin of the device. see the functionality table at the beginning of this data sheet for a list of the specific frequencies that this clock operates at and the selection codes that are necessary to produce these frequencies. fs0, fs1, fs2 these pins control the frequency of the clocks at the cpu, cpul, bus, sdram, agp and ioapic pins. see the fun- tionality table at the beginning of this data sheet for a list of the specific frequencies that this clock operates at and the selection codes that are necessary to produce these frequencies. the device reads these pins at power-up and stores the programmed selection code in an internal data latch. (see programming section of this data sheet for configuration circuitry recommendations. bsel when this pin is a logic 1, it will place the cpu clocks in the synchronous mode (running at half the frequency of the ref). if this pin is a logic 0, it will be in the asynchronous mode for the cpu clocks and will operate at the preprogrammed fixed frequency rate. it is a shared pin and is programed the same way as the frequency select pins. vdd 2, 3 these are the power supply pins for the cpu clock buffers. by separating the clock power pins, each group can receive the appropriate power decoupling and bypassing necessary to minimize emi and crosstalk between the individual signals. vdd2 can be reduced to 2.5v vdd for advanced processor clocks, which will bring cpu (1:6) outputs at 0 to 2.5v output swings. 48 mhz this is a fixed frequency clock that is typically used to drive super i/o peripheral device needs. 24 mhz this is a fixed frequency clock that is typically used to drive keyboard controller clock needs. vdd4 this power pin supplies the bus clock buffers. ref this is a fixed frequency clock that runs at the same frequency as the input reference clock (typically 14.31818 mhz) is and typically used to drive video and isa bus requirements. vdd5 this power pin supplies the 48/24 mhz clocks.
6 ics169c-232 absolute maximum ratings electrical characteristics at 3.3v supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd C0.5 v to v dd +0.5 v ambient opera ting t emperature . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . C65c to +150c v dd = 3.0 C 3.7 v, t a = 0 C 70 c unless otherwise stated note 1: parameter is guaranteed by design and characterization. not 100% tested in production. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc characteristics parameter symbol test conditions min typ max units input low voltage v il - - 0.2v dd v input high voltage v ih 0.7v dd --v input low current i il v in = 0v -28.0 -10.5 - a input high current i ih v in = v dd -5.0 - 5.0 a output low current 1 i ol v ol = 0.8v; for cpu, bus, ref clks 19.0 30.0 - ma output high current 1 i oh v ol = 2.0v; for cpu, bus, ref clks - -38.0 -16.0 ma output low current 1 i ol v ol = 0.8v; for fixed clks 16.0 25.0 - ma output high current 1 i oh v ol = 2.0v; for fixed clks - -30.0 -14.0 ma output low voltage 1 v ol i ol = 10ma; for cpu, bus, ref clks - 0.3 0.4 v output high voltage 1 v oh i oh = -15ma; for cpu, bus, ref clks 2.4 2.8 - v output low voltage 1 v ol iol = 8ma; for fixed clks - 0.3 0.4 v output high voltage 1 v oh i oh = -8ma; for fixed clks 2.4 2.8 - v supply current i dd @66.6 mhz; all outputs unloaded - 70 140 ma
7 ics169c-232 electrical characteristics at 3.3v v dd = 3.0 C 3.7 v, t a = 0 C 70 c unless otherwise stated note 1: parameter is guaranteed by design and characterization. not 100% tested in production. ac characteristics parameter symbol test conditions min typ max units rise time 1 t r1 20pf load, 0.8 to 2.0v cpu & bus - 0.9 1.5 ns fall time 1 t f1 20pf load, 2.0 to 0.8v cpu & bus - 0.8 1.4 ns rise time 1 t r2 20pf load, 20% to 80% cpu & bus - 1.5 2.5 ns fall time 1 t f2 20pf load, 80% to 20% cpu & bus - 1.4 2.4 ns duty cycle 1 d t 20pf load @ vout=1.4v 45 50 60 % jitter, one sigma 1 t j1s1 cpu & bus clocks; load=20pf, bsel=1 - 50 150 ps jitter, absolute 1 t jab1 cpu & bus clocks; load=20pf, bsel=1 -250 - 250 ps jitter, one sigma 1 t j1s2 ref & fixed clks; load=20pf - 1 3 % jitter, absolute 1 t jab2 ref & fixed clks; load=20pf -5 2 5 % input frequency 1 f i 12.0 14.318 16.0 mhz logic input capacitance 1 c in logic input pins - 5 - pf crystal oscillator capacitance 1 c inx x1, x2 pins - 18 - pf power-on time 1 t on from v dd =1.6v to 1st crossing of 66.6 mhz v dd supply ramp < 40ms - 2.5 4.5 ms frequency settling time 1 t s from 1st crossing of acquisition to < 1% settling - 2.0 4.0 ms clock skew 1 t sk1 cpu to cpu; load=20pf; @1.4v - 150 250 ps clock skew 1 t sk2 bus & bus; load=20pf; @1.4v - 160 500 ps clock skew 1 t sk3 cpu to bus; load=20pf; @1.4v (cpu is early) 1 2.6 4 ns
8 ics169c-232 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ordering information ics9169cf-232 ics9169cm-232 ssop package example: ics xxxx f - ppp ssop symbol common dimensions ssop variations d min. nom. max. min. nom. max. a 0.068 0.073 0.078 14 0.239 0.244 0.249 a1 0.002 0.005 0.008 16 0.239 0.244 0.249 a2 0.066 0.068 0.070 20 0.278 0.284 0.289 b 0.010 0.012 0.015 24 0.318 0.323 0.328 c 0.004 0.006 0.008 28 0.397 0.402 0.407 d see variations 30 0.397 0.402 0.407 e 0.205 0.209 0.212 e 0.0256 bsc h 0.301 0.307 0.311 l 0.025 0.030 0.037 n see variations 0 4 8 soic package lead count 14l 16l 18l 20l 24l 28l 32l dimension l 0.354 0.404 0.454 0.504 0.604 0.704 0.804 soic package (wide body) e = 0.05 bsc
|
